Plasma Technology for Advanced Devices
Recent Developments in Exreme Ultraviolet (EUV) Lithography
IBM extends immersion lithography
February 28, 2007
EUV: Who gets the first tool ?
September 5, 2006
The full press release can be found on BNR Nieuwsradio. Here is an excerpt of it:
ASML announced on 8/29 that it shipped two extreme ultraviolet (EUV) Alpha Demo Tools to customers. Both the College of Nanoscale Science and Engineering (CNSE) of the State University of New York (SUNY) at Albany, N.Y., and the nanoelectronics research institute IMEC in Leuven, Belgium, have received these industry first, full field EUV systems. Both institutions will use these R&D tools after installation to conduct ongoing research into this next generation lithography technology. Shipments were possible after ASML achieved key lithography performance targets including full field scanning imaging and overlay. Martin van den Brink, executive vice president, marketing and technology at ASML said: "While these tools are research systems, pre-production EUV lithography tools could be shipped as early as 2009 depending on customer commitment." The company considers EUV as the most attractive technology for 32 nm and beyond, because of its potential to be the most cost effective technology and its extendibility to multiple nodes. Earlier this year at the SPIE Microlithography conference the company presented proof-of-concept 35-nm resist images obtained over a full slit of 26 mm, made on one of these systems. ASML expects that these alpha demo tools to be essential in developing the infrastructure for EUV lithography.
The shipments to IMEC and Albany expose EUV to a large number of potential users. The lithogrpahy program at IMEC has more than 30 partners including Infineon, Intel, Matsushita/Panasonic, Micron, Philips Semiconductor, Samsung, STMicroelectronics, Texas Instruments and TSMC. The mambers of the College of Nanoscale Science and Engineering include AMD, IBM, Micron Technology and Qimonda. Sony and Toshiba.
EUV is at this point in time the most likely candidate technology for the 32nm half-pitch node. NE Asia reports that IMEC's EUV program includes investigation of several areas: optical path stability and monitoring; EUV lithography reticle handling (including cleaning) in a wafer fab and defect printability; assessment of line-edge roughness (LER) in EUV lithography and its relation to shot noise; EUV lithography resist assessment and process optimization; (sub-)32nm node critical layer patterning; and printable defects of EUV masks.