Plasma Technology for Advanced Devices

Influence of Mask Marterials in Silicon Gate Etching

The choice of the mask material for silicon gate etching depends on the process requirements. These materials can be grouped into carbon based materials (photoresists, bottom anireflective coatings (BARC) and carbon hardmasks) and silicon based dielectric masks (oxides, nitride, dielectric antireflective coatings (DARC)).

Slide 1 shows results of ellipsometry studies of the influence of the mask materials on the gate oxide etch rate. Under identical process conditions (HBr/Cl2/O2 standard chemistries), the gate oxide consumption is increased by a factor of 4 when going from a hardmask to a resist mask. This corroborates the common notion that resist masks tend to impact gate oxide selectivity negatively.

One possible explanation for the lower gate oxide selectivity is that carbon is liberated from the resist mask during the etch process and deposited on the gate oxide. Oxide tends to etch faster in the presence of carbon due to the formation of volatile carbon oxides. In-situ XPS studies of the gate oxide surface show that while Carbon is present on the gate oxide with the resist mask it is absent on the gate oxide with the SiO2 hardmask (slides 2 and 3).

The loss of gate oxide loss and the carbon concentration on the gate oxide surface both increase with the local resist coverage. When etching resist masked poly silicon gates, the poly-Si/SiO2 selectivity across the wafer is strongly affected by the local resist coverage (slide 4).

Besides concerns concerns about the gate oxide selectivity, other reasons to use dielectric hardmasks in advanced gate etching include the dramatically reduced resist thickness / budget for advanced gate etching as well as mask charging (slide 5).

In-situ reflectometry measurements with a commercial predictive endpoint system provide additional evidence that the gate oxide erodes faster in the presence of photoresists on the wafer. In addition, the experiment reveals that the presence of silicon also lowers the gate oxide selectivity. This effect is smaller than for resist but measurable. A very uniform etch rate across the wafer is therefore mandatory to avoid local gate oxide pitting or punch through (slide 6).

Advanced poly-Si gate stack for high performance devices are frequently doped. Fluorine addition is frequently used to reduce the doping effect in advanced gate etching. CF4 addition is much more efficient than non-carbon containing gases like NF3. With respect to dielectric hardmasks, this has a double negative impact on mask selectivity: Both fluorine and carbon increase the oxide or nitride etch rate and lower therefore the mask selectivity (slide 7).

The need for fluorocarbon addition drives the resurgence of resist schemes and the emergence of carbon and other alternative hardmasks (slide 8).

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