Plasma Technology for Advanced Devices

High k Etch
from: "Plasma Etching Challenges of new materials involved in Gate Stack Patterning for sub 45 nm Technological Nodes"
O. Joubert, A. Legouil, R. Ramos, M. Helot, O. Luere, E. Richard, G. Cunge, T. Chevolleau, E. Pargon and L. Vallier (LTM-CNRS, Grenoble, France)
T. Morel and S. Barnola (CEA-LETI, Grenoble, France)
T. Lill, J. Holland and A Patterson (Applied Materials, Sunnyvale, CA, USA)
Presented at AVS 2006

One of the main requirements for etching of high k dielectrics is excellent selectivity to silicon. For logic gates, this translates into the request for zero silicon recess in the source / drain area. During HfO2 deposition a thin SiO2 interfacial layer is always formed between the silicon substrate and HfO2 layer. This means that in order to achieve zero recess, one has to stop on this very thin silicon oxide interface layer.

Using a Cl2/CO gas chemistry at low pressure, high wafer temperature and without bias power applied to the wafer, the HfO2 etch rate is about 100 A/min and the selectivity towards SiO2 is about 20 (slide 1). The process is very sensitive to the ion energy: at 25 W bias power, the selectivity towards SiO2 drops to less than 3.

XPS analyses show that without bias power applied to the wafer, the HfO2 layer is free from any deposits, i.e. etches, while a CClx layer is formed on SiO2. This means that the selectivity towards SiO2 is obtained thanks to the formation of the CClx deposition layer on top of the thin interfacial SiO2 layer.

Slide 2 shows the integration of HfO2 polysilicon and oxide hardmask on a patterned wafer. The film stack is comprised of 40 nm thick SiO2 HM, 100 nm polysilicon and 3.5 nm HfO2. The wafers were patterned using e-beam lithography. High resolution TEM pictures of the etched structures are shown. The gate exhibits a straight profile with a slight notch at the bottom of the gate. This results show that the high temperature HfO2 etch process does not induce any profile distortion of the silicon gate. A HfO2 foot at the bottom of gate requires more process optimization. The silicon recess is approximately 3 nm.

Slide 3 shows the bias power dependence of a BCl3 based low temperature high k etch process. At 800 W source power, Si and SiO2 show deposition of BClx based polymers for bias powers between 0 and 7 W and etch above bias powers of 7 W. HfOx etches for all bias powers which results in an infinite HfOx to Si and SiOx selectivity for bias powers between 0 and 7 W. It is quite obvious that the bias power had to be very well controlled for this process. Also, even small deviations in the crystalline structure or composition of the HfOx material (for instance additions of Ak or Zr) can lead to dramatically reduced selectivities and residues. In this respect, the high temperature process has a larger process window.

The etch rate observations for the BCl3 room temperature process in slide 3 can be corroborated by XPS surface composition studies of SiOx and HfOx (slide 4). The surface of SiOx shows a deposition layer for SiOx for 0 and 10 W bias power. The layer is thicker for 0 W. The deposition layer for HfOx at 0 W is similar to the layer on the SiOx surface at 10 Wb. At 10 W, only traces of B and Cl can be found on the HfOx surface which is indicative of a surface that has been etched.

The BCl3 room temperature process is quite sensitive to chamber wall effects. Slide 5 shows how the SiOx etch rate changes as a function of chamber wall coverage for 10 Watt bias power: carbon coated vs. SiOxCly coated vs. cleaned walls (AlFx). When the chamber walls are coated with carbon, etch stop occurs due to polymer deposition. This is important when complex stacks are being etched. The same recipe may show good selectivity after a fluorocarbon based etch step and show punch through after a dry clean or HBr/Cl2 based silicon etch.

Slide 6 shows the same experiments as slide 5 for the etch rates of HfOx. The rate is the highest for the clean wall, followed by the carbon coated wall. The etch rate for the SiOxClx coated wall is much lower but etch stop does not occur. Note that for the SiOx layer, carbon coating had the strongest effect on etch rate suppression. One possible explanation is that carbon coated chamber walls are loading chlorine species leading to an increase of the BClx layer thickness on top of the HfOx due to the absence of etching species.

Slide 7 shows a metal gate / high k stack containing poly-Si on top of TiN followed by WN on HfOx. Zero silicon recess was achieved with the room temperature BCl3 process. The WN profile is tapered and required some more process optimization.

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