Plasma Technology for Advanced Devices
Volume 1: September 2002
“Formation of Ammonium Salts and Their Effects on Controlling Pattern Geometry in the Reactive Ion Etching Process for Fabricating Aluminum Wiring and Polysilicon Gate”
This paper studies the effect of nitrogen addition to chlorine based Al and HBr / Cl2 based poly-Si chemistries. In both cases, the addition of nitrogen leads to more tapered (or less notched) profiles. While this effect is well known and used in industrial scale production, the passivation mechanism for nitrogen addition is not understood. In the case of poly-Si etching, the formation of silicon nitride reaction products on the feature sidewalls had been proposed previously. Saito and coworkers use FT-IR, AES, XPS and TDS surface analysis methods to show that the ammonium salts such ass NH4AlCl4 in the case of Al etching and (NH4)2SiBr6 in the case of poly-Si etching are formed on the feature sidewalls. The source of hydrogen is the resist in the case of Al etching and HBr in the case of hardmask WSix/Si stack etching.
Modeling of Plasma Etching
“Multiscale Modeling of Plasma Etch Processing”
This paper gives a very good overview of the status of multi-scale modeling of plasma assisted semiconductor processing. Commercial reactor, sheath and feature scale models are presented. The author points out that the proper link between the simulation models has not yet been deployed. Feature scale feedback is an outstanding issue.
“Diagnostics of a Wafer Interface of a Pulsed Two-Frequency Capacitively Coupled Plasma for Oxide Etching by Emission Selected Computerized Tomography”
This paper reports results of Computerized Tomography (CT) measurements of an interface close to a SiO2 wafer being etched in a 2f-CCP system. CF4/Ar and Ar plasmas at 25 mTorr are sustained with 100 MHz VHF source power which is pulsed. The bias power has a frequency of 500 kHz. The experimental results predict that the double layered sheath structure is interacting with the wafer biased with a low frequency RF field. Negatively charged particles can be accelerated to the wafer surface from the CF4/Ar plasma under these conditions. Feature sidewall neutralization by negatively charged ions is be a desired effect in high aspect ratio dielectric etching.
“ Measurements and Modelling of Ion Energy Distributions in High-Density, Radio-Frequency Biased CF4 Discharges”
Ion energy distributions (IED’s) for 10 mTorr high density ICP CF4 plasmas have been measured. The ion energies were measured with a grounded energy analyzer / mass spectrometer, i.e. the IED’s were measured for the grounded walls, not the biased cathode. Biasing effects could be measured due to the additional voltage developed across the ground sheath when bias power is applied. The measurements show good agreement with a sheath model described previously. Input parameters (time averaged current density and plasma potential) were measured with the experimental setup. The electron temperature was taken from the literature. The model was found to predict IED’s well for the entire range of bias frequencies, even for intermediate frequencies when the ion transit time is comparable to the RF bias period.
“Impact of Floating Gate Dry Etching on Erase Characteristics in NOR Flash Memory”
The impact of plasma damage effects on erase characteristics of flash memory cells has been investigated. The effect of fast erasing bits could be traced back to plasma damage effects in a non optimized plasma during the floating gate etch process. The experimental results indicate that the physical effect responsible for the fast erasing bits are clusters of positive charges near the poly-Si / SiO2 interface.
“The Vertical Replacement-Gate (VRG) MOSFET”
A very detailed description of the formation and integration of vertical replacement gate (VRG) MOSFET’s. The VRG-MOSFET is aimed at memory as well as at high performance and high speed logic. High performance devices with 50 nm physical gate length have been demonstrated without advanced lithography. The key features of this device are a gate oxide that is grown on single crystal silicon, self-aligned source/drain extensions formed by solid source diffusion, small parasitic overlap, junction, and source/drain capacitances, as well as a replacement gate approach that enables alternative stacks.
“FinFET Desgin Considerations Based on 3-D Simulation and Analytical Modeling”
3D simulations of FinFET devices are presented. The moel predicts a bump in the drain voltage vs. gate current curve that is caused by corner effects of the silicon sliver that represents the Fin. The elimination of these corners could be a technological challenge.