Plasma Technology for Advanced Devices


Volume 21: December 2005
IEDM 2005

High Performance 65 nm SOI Technology with Enhanced Transistor Strain and Advanced-Low-K BEOL
W.-H. Lee et al.

This paper by a joint team from IBM, Toshiba and AMD presents a high performance 65 nm SOI CMOS technology. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are used. An embedded SiGe process is implemented with epitaxial SiGe growth in cavities etched into the source/drain areas of the pFETs. The nFETs are covered with a nitride hardmask during recess etch and epitaxial growth of SiGe in the pFET areas. This technology delivers pFET and nFET AC switching on-current of 735 uA/um and 1259 uA/um respectively, at an off-current of 200 nA/um (Vdd=1.0 V) for a gate oxide thickness of 1.05 nm. The threshold voltage roll-off is well-behaved down to 30 nm gate length, and sub-threshold swing is maintained at ~110 mV/dec.

For transistor performance comparison, follow this link.

Improved Sub-10-nm CMOS Devices with Elevated Source/Drain Extensions by Tunneling Si-Selective-Epitaxial-Growth
H. Wakabayashi et al.

This paper by NEC investigates sub-10nm CMOS devices with elevated source/drain extensions (eSDE) using the tunneling silicon selective epitaxial growth (Si-SEG) in the reverse-order source/drain formation. The thickness for eSDE region is precisely controlled by the self-limited Si-SEG process within a narrow slit underneath a SiN sidewall film. The SEG-Si film for the elevated source/drain (eS/D) region is formed simultaneously. Due to reduced short-channel effect and parasitic resistance, the Ioff-CV/I characteristics are remarkably improved for both n- and pMOSFETs, as compared with published sub-10-nm planar bulk CMOS devices.

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High Performance 35nm Lg CMOS Transistors Featuring NiSi Metal Gate (FUSI), Uniaxial Strained Silicon Channels and 1.2nm Gate Oxide
P. Ranade et al.

This paper by Intel describes highly strained silicon CMOS transistors with NiSi metal gate electrodes and ultra-thin 1.2nm gate oxide. The primary advantage of using Ni for full gate silicidation is the low temperature needed to form NiSi which enables FUSI gate formation post junction activation. Performance gains from FUSI gate stack and uniaxial strained Si channels are demonstrated to be fully additive and enable high drive currents – NMOS Idsat=1.75mA/um, PMOS Idsat=1.06 mA/um (Vdd=1.2V, Ioff=100nA/um).

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High Performance CMOS Bulk Technology Using Direct Silicon Bond (DSB) Mixed Crystal Orientation Substrates
Chun-Yung Sung et al.

This paper by IBM presents another evolution of the hybrid orientation technology. In previous work, the integration of CMOS with hybrid orientation substrates was done via a wafer bonding and selective silicon epitaxy process. The resulting device structures had a mixture of bulk and SOI devices, which introduces process integration and circuit design complexity. In this work, high performance 65-nm technology (Lpoly=45nm, EOT=1.2nm) bulk CMOS has been demonstrated on mixed orientation substrates formed by using direct silicon bonded (DSB) wafers and a solid phase epitaxy (SPE) process which produces an oxide free interface between the differently oriented Si layers. Solid phase epitaxy is used to convert the orientation of nFET regions from (110) to (100): the nFET regions are amorphized to a depth beyond the bonded interface and then converted to a (100) orientation by solid phase epitaxy from the (100) substrate. The pFET performance is improved by 35% due to hole mobility enhancement on (110) surfaces as compared to (100) surfaces. nFETs on SPE-converted (100) surfaces exhibit the same performance as those on (100) controls. Ring oscillators fabricated using DSB with SPE show improvements of more than 20% compared with control CMOS on (100) surfaces.

For transistor performance comparison, follow this link.

High Performance 30 nm Gate Bulk CMOS for 45 nm Node with Sigma-shaped SiGe-SD
H.Ohta et al.

Aggressively scaled 30 nm gate CMOSFETs for the 45 nm node is reported by Fujitsu. A Sigma-shaped SiGe Source/Drain (SiGe-SD) structure improved the short channel effect while maintaining a high drive current. Both hole mobility and Source/Drain Extension (SDE) resistance in pMOSFET are improved by combination of optimized Σιγμα-shaped SiGe-SD and slit-embedded B-doped SiGe-SDE. The gate poly-Si height of the pMOS transistor was aggressively scaled down in order to reduce the high tensile stress from the nitride cap film, which suppresses the reduction of hole mobility by the tensile stress. The Sigma-shaped SiGe-SD increases the channel stress up to 100 % compared to that of a normal (box or U-shaped) recess. A normal shaped recess was formed by using conventional dry etch process which has an anisotropic nature. In contrast, the Sigma-shaped recess was formed by a post-treatment after dry etch process. After SD etching, a B-doped SiGe-SD was re-grown. High performance 30 nm/33 nm gate nMOSFET’s and pMOSFET’s were demonstrated with a drive currents of 937/1000 uA/um and 490/545 uA/um at Vd=1.0 V / Ioff=100 nA/um, respectively for a plasma nitrided gate oxide with an EOT of 1.2 nm. Well controlled subthreshold slopes of 100 mV/dec and 103 mV/dec were obtained for nMOS and pMOS, respectively. The smallest CV/I value of 0.59 ps was observed at Lmin for the 30 nm nMOSFET. The smallest CV/I value of 0.99 ps was observed at Lmin of 30 nm pMOSFET with Sigma-shaped SiGe-SD.

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Design of High Performance PFETs with Strained Si Channel and Laser Anneal
Z. Luo et al.

In this paper by IBM, Chartered, Infineon, and Toshiba, the effects of the integration of two major PFET performance enhancers, eSiGe junctions and compressively stressed nitride liner (CSL) have been examined. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 640 uA/um at 50 nA/um off state current at 1V) with only modest Ge incorporation (~20 at. %) in S/D (Lgate=43nm and Tox=11). A selective recess etch process was developed to etch the S/D regions of PFETs, while maintaining the integrity of the gate and the S/D extension regions. In an e-SiGe only process, extremely tight control of the variation in the e-SiGe thickness is required, because the e-SiGe thickness variation normally results in a large variation of the channel. It was found that integrating CSL with e-SiGe can significantly reduce device variations caused by the e-SiGe thickness variation, thereby making the e-SiGe process more manufacturable. The paper demonstrates that by integrating e-SiGe and laser anneal (LA), defect-free e-SiGe can be fabricated, and the benefits of both techniques can be retained. The study of geometric effects also reveals that e-SiGe can be extended to 45 nm technology and beyond.

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Inverted T channel FET (ITFET) – Fabrication and Characteristics of Vertical-Horizontal, Thin Body , Multi-Gate , Multi-Orientation Devices, ITFET SRAM Bit-cell operation. A Novel Technology for 45nm and Beyond CMOS
L. Mathew et al.

This paper by Freescale and the University of Florida demonstrates a novel CMOS IT-FET (Inverted T Channel FET) architecture. The ITFET is novel device architecture that takes advantage of both vertical and horizontal thin-body devices. A doped channel IT-FET process has been developed. This technology can be scaled beyond 45nm Technologies using undoped channels. An ITFET device comprises of an Ultra thin body planar horizontal channels and vertical channels in a single device. The devices have multi-gate control around these channels to improve short channel control. A single device has multiple orientations and hence mobility enhancement of both (110) and (100) planes can be used optimally. The devices presented have 15nm planar horizontal thin body and 40 nm vertical Channels of 100 nm height, 17 gate dielectric and 50nm gate length. The process flow to fabricate ITFET uses traditional SOI process integration. The paper lists the following advantages of ITFET's:
1) Thin Body for gate control: Since both the vertical and horizontal channel regions use thin body region short channel characteristic are well controlled.
2) Layout Efficient: Between fins there is no inactive regions, leads to maximum use of layout, the effective width/pitch is better than FinFET and planar devices.
3) Surface Mobility Optimization: The surface orientation of the ITFET device is a combination of the top and sidewall surfaces both can be optimized by design and initial process.
4) Width Granularity: The granularity of the channel width in an ITFET can be varied by The Horizontal region in the ITFET can be defined during design.
5) Reduced Parasitics: The Cj/Width is lower in ITFET, Silicide of Fin and horizontal regions reduce parasitic resistance, the backend interconnect RC is lower since the area/width is lower in ITFET devices.
6) Scaling: Further scaled ITFET devices using metal gates can take advantage of undoped channels and doped horizontal regions.

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High Performance 5nm radius Twin Silicon Nanowire MOSFET(TSNWFET): Fabrication on Bulk Si Wafer, Characteristics, and Reliability

S. D. Suk et al.

This paper by SAMSUNG presents a gate-all-around Twin Silicon Nanowire Transistor (TSNWFET) on bulk Si wafer with 2 nm gate oxide using a self-aligned damascene-gate process. For 10nm diameter nanowires, saturation currents through twin nanowires of 2.64 mA/um and 1.11 mA/um for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. The off-currents were 3.1 nA/um and 5.6 pA/um for the n- and p-channel devices, respectively. No roll-off of threshold voltages, ~70 mV/dec of substhreshold swing (SS), and ~20 mV/V of Drain Induced Barrier Lowering (DIBL) down to 30 nm gate length are observed for both n-channel and p-channel TSNWFETs. In order to scale down the gate length of TSNWFET aggressively without the help of sophisticated lithography tools, a damascene-gate process was used. Optionally, an additional H2 anneal process was applied to get a circular cross-sectional shape of the nanowires. The p-channel TSNWFET used TiN as gate material.

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Process Integration Technology and Device Characteristics of CMOS FinFET on Bulk Silicon Substrate with sub-10 nm Fin Width and 20 nm Gate Length
K. Okano et al.

This paper by Toshiba discusses the process integration technology and the device characteristics of CMOS bulk-FinFET's to realize the miniaturization of both fin width and gate length. A new trimming technique by oxidation is used to form very narrow fins. The silicon fin and SiN cap were simultaneously oxidized almost the same amount by a newly developed plasma oxidation technique. After fin formation, the shallow device isolation region is formed by HDP SiO2 fill and CMP. Then the planarized HDP SiO2 is etched back to the half height of the fin. Thus the tail of tapered structure of the fin is embedded in the HDP SiO2 and the degradation of the punch through immunity can be alleviated. Simulations show that some portion of the leakage current flows beneath the channel region that is embedded in HDP SiO2. In order to suppress this leakage current, it is necessary to introduce punch through stopper (PTS) structure at the channel bottom region of bulk-FinFET. In a newly proposed PTS formation technique, ions are implanted at 0 deg tilt angle into the half-etched HDP SiO2 region with much lowered implantation energy than that of the conventional PTS formation method. Under these conditions, implanted ions are scattered in the HDP SiO2 region and some portion of the laterally scattered ions penetrate into the fin region. Subsequently, the ion implant condition for source/drain formation have to be optimized in order to avoid breaking the PTS region.

The paper reports drive currents of 800 mA/um at Vd=1.0 for both n-FinFET and p-FinFET with 10 nm fin width and 30 nm gate length. For the same fin width, the subthreshold slope is around 80 mV/dec.

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Damage-Free Neutral Beam Etching Technology for High Mobility FinFETs
Kazuhiko Endo et al.

In this paper by AIST and the Tohoku University, neutral beam (NB) and conventional reactive ion etching were used to fabricate high aspect rectangular Si-fins. As for the NBE, a chlorine-based gas chemistry was used and a pulse-time modulated rf (13.56 MHz, on-time/ off-time= 50 ms/ 100 ms) power was applied to generate the plasma. Negative ions are accelerated from the plasma and neutralized by passing through the apertures in the carbon bottom plate. Cross-sectional high resolution TEM Indicate that the NB process can accomplish a defect-free and atomically smooth sidewall surface, whereas the chlorine based RIE processes shows crystal defects and surface roughness. It is noteworthy that the RIE process was chlorine based and it is not reported whether any process optimization was performed to reduce sidewall roughness and defects. The FinFETs fabricated with neutral beam etching realized higher electron mobility than that using a conventional reactive ion etching. The improved mobility is explained by the NB etched atomically-flat surface.

High Performance nMOSFET with HfSix/HfO2 Gate Stack by Low Temperature Process
T. Hirano et al.

In this paper by Sony, HfSix/HfO2 gate stacks by low temperature process are reported to reduce mobility degradation caused by bulk traps or plasma damage with the excellent Vth controllability. No interface layer was observed. A drive current of 1.25mA/um at the off-state leakage of

1nA/μm was obtained at Vdd=1.3V with 65nm gate length and 1.6 nm Tinv nMOSFETs without strain enhanced technology.

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