Plasma Technology for Advanced Devices

Metal Gate Etch
from: "Plasma Etching Challenges of new materials involved in Gate Stack Patterning for sub 45 nm Technological Nodes"
O. Joubert, A. Legouil, R. Ramos, M. Helot, O. Luere, E. Richard, G. Cunge, T. Chevolleau, E. Pargon and L. Vallier (LTM-CNRS, Grenoble, France)
T. Morel and S. Barnola (CEA-LETI, Grenoble, France)
T. Lill, J. Holland and A Patterson (Applied Materials, Sunnyvale, CA, USA)
Presented at AVS 2006

After several years of intensive research, the IC industry is about to introduce metal gates for logic devices. New materials carry significant risks for manufacturability and reliability which seem to be justified by their benefits. Metal gates can reduce the depletion effect in p-Si, decrease the gate resistivity and minimize the dopant diffusion (slide 1). For the 45 nm node and below, the industry may move from the dual doped polysilicon gates to various types of metal gate architecture. In the mid gap approach, a single metal such as TiN can be used. In the dual metal gate architecture, one n-type metal (for instance TaN) and a p-type metal (for instance WN) will be used. In the following study, we focus on the formation of TiN and TaN metal gates via substractive formation by plasma etching.

Another application of novel materials is the use of high k materials for metal gates. When the length of the gate decreases, the gate oxide capacitance must increase. With SiO2 this is achieved by decreasing the SiO2 thickness. This eventually leads to exceedingly high leakage currents which are induced by electron tunneling through the gate oxide (slide 2).

High k dielectric materials are introduced to obtain the same gate oxide capacitance with a thicker dielectric layer which in turn allows much less leakage current.

In this work, we have studied the formation of advanced transistor gates with hafnium based dielectric materials.

The main challenges for etching of metal gates and high k dielectrics are shown in slide 3 for a typical gate stack with 3 nm high k, a 10 nm thick metal layer a 50 to 100 nm thick polysilicon layer on top.

The first steps of the process are devoted to the formation of a thin hard mask such as SiO2 or amorphous carbon. The gate stack (p-Si and metal) is patterned with specific steps to preserve the gate dielectric integrity. In a final step, the high k dielectric layer is removed using soft plasma conditions to minimize the silicon recess.

In this sequence of etch steps, the main challenge is to obtain sub 30 nm gate structures with a CD control better than 2 nm across 300 mm diameter wafers.

Slide 4 shows the experimental setup which uses an industrial 200 mm etch platform with two ICP sources (Applied Materials DPS HT and DPS Plus). Both chambers are used for the etching of silicon, metal and oxide materials. The main difference between these two chambers is the chuck temperature. The DPS Plus operates at chuck temperatures between 10 and 80 C and the DPS HT reaches temperatures between 150 and 300C. A real time process control is possible using interferometry and optical emission.

An XPS surface analysis chamber is connected to the etch platform allowing quasi in situ analysis of etched wafers. This is a very powerful technique giving the chemical and surface composition of the reactive layers formed during plasma exposure.

In-situ XPS allows the the analysis of chamber wall deposits via air gap technique (slide 5). A sample representing the chamber material (for instance Al2O3 or Y2O3) is mounted on top of a carrier wafer. The gap height is chosen such that the bias at the sample surface is reduced to a value equal to the selfbias at the reactor walls (typically 15 eV). When the plasma is turned on, the wafer surface is etched and the reaction by-products get deposited at the sample surface. The composition of the deposits can be analysed quasi in-situ after the wafer is transferred to the analysis chamber without breaking vacuum.

Metals can be etched with halogen gas mixtures. Titanium forms volatile chlorides and bromides while titanium fluoride is relatively less volatile. Like in the case of silicon etching, oxygen addition can provide a means for effective sidewall passivation. However, when oxygen is used for etching titanium or titanium nitride, residues can readily be observed (slide 6). In situ XPS analysis reveals, that the residues are comprised of titanium oxides. The formation of oxides which are hard to remove is fairly common in etching of various metals. Oxygen as a passivation gas has to be used very carefully or avoided altogether.

Slide 7 shows, that when HBr is the main etch gas in a HBr/Cl2 gas mixture, sidewall passivation is obtained without the addition of any oxygen (note tapered TiN profiles. With careful optimization of the HBr/Cl2 ratio, good selectivities towards HfO2 and a good CD control can be obtained. However, a slight notch is observed at the bottom of the silicon part of the gate. Partitioning experiments revealed, that the notch is formed during the TiN etch process. The formation of this notch will be studied in the following.

XPS analysis of the polysilicon sidewall before and after the TiN etch step reveals significant differences in the composition of the sidewall (slide 8). Before TiN etching the sidewall contains 21% silicon atoms bound not to other silicon atoms, 32% oxygen, 15% chlorine and 7% bromine atoms, i.e. it is comprosed of silicon oxyhalogenides. After the TiN step, the thickness of the passivation layer is significantly reduced (poly-Si signal increased from 25 to 53%). The formation of the notch at the silicon / TiN interface can be attributed to the erosion of the passivation layer during TiN etching in oxygen free chemistries. The passivation payer formed on the silicon didewalls must be preserved during metal etching.

Slide 9 shows how the choice of an appropriate polysilicon etch chemistry provides better compatibility with the TiN etch process. Two silicon etch chemistries have been compared: a traditional HBr/Cl2/O2 process and a fluorine based SF6/CH2F2 process where the passivation is achieved by fluorocarbon polymer formation on the sidewalls. The results indicate, that the fluorocarbon pasivation provides much better protection than the silicon oxyhalogenide passivation of the traditional gate etch process. The metal etch chemistry is driving the choice of the polysilion gate etch chemistry.

Tantalum nitride can be etched with HBr. Depending on the process conditions, very thick sidewall passivation layers can be formed on the tantalum and polysilicon layers (slide 10). This can lead to tapered TaN profiles.

The composition of the sidewall layer after etching of TaN with HBr can be measured directly with XPS or be derived from the composition of the chamber wall deposits. XPS studies were performed with the air gap method to identify the coatings formed on the chamber walls. Slide 11 shows that after silicon etching, a thin SiOxCly deposit is formed on the chamber walls. After TaN etching, a thick TaOxBry layer coats the reactor walls demonstrating that heavy non-volatile Ta based etch by-products are deposited on all the surfaces exposed to the plasma.

To avoid very thick Ta based chamber wall and sidewall deposition, chlorine and fluorine based chemistries seem to be promising. Slide 12 shows that more vertical profiles be achieved with a Cl2/CF4 mixture. In low pressure CF4/Cl2 plasmas, almost vertical TaN profiles and good selectivity to HfO2 are obtained. However, the presence of fluorine in the gas phase induces a severe profile deformation in the top silicon part of the gate, indicating that the SiOxBry based passivation formed on the silicon sidewalls is completely removed by fluorine species.

These results highlight the critical importance of the compatibility between the etch chemistries used to pattern the top silicon part and bottom metal part of the gate stack.

Slide 13 shows results of etch chemistry studies for a polysilicon / WN stack. The polysilicon has been etched with a traditional HBr and Cl2 based process where the sidewall passivation is achieved via the formation of silicon oxyhalogenides. The TEM’s show that a Cl2 based WN process produces a strong WClx layer which gets deposited on the polysilion profile and provides additional passivation. The resulting WN profile is tapered. When CF4 is used to etch WN, the free fluorine removes the polysilicon sidewall passivation layer and start to etch sideways into the polysilicon. The WN is also tapered, either because of a lack of directionality (isotropic etch) or because of the passivating effect of carbon. The Cl2 based WN etch is the better choice but needs to be optimized to obtain directionality.

Slide 14 shows the compositions of chamber wall deposits for WN and WSix etched with fluorine, chlorine and bromine based chemistries. When WN is etched with an SF6/CH2F2 mixture, an AlFx layer is formed. The etching of WSix with chlorine generates WSixCly deposits while HBr forms a very thick WBrx layer on the chamber walls. The thickness of the chamber wall deposition correlates roughly with the volatilily of the etch by-products. In any case, appropriate waferless dry cleans have to be developed to avoid by-product accumulation and particle generation.

The dry clean recipe has to be designed for each metal material / etch chemistry combination. Slide 15 shows that SF6/O2 dry cleans remove TiOxCly deposits which were formed when TiN was etched with a Cl2/O2 process. In the process, AlFx is formed on the chamber walls. An CF4/Cl2 mixture removes TaOxBry residues from etching of TaN with an HBr chemistry. The dry cleans also needs to take into condiration residues from other layers of the gate stack, for instance BARC, hardmask and polysilicon layers.

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