Plasma Technology for Advanced Devices

Clarycon News Archive: IBM

IBM and its alliance partners Chartered, Samsung, Infineon, and Freescale will extend their collaboration to the 32nm node. The program is scheduled to last through 2010 and will be conducted at the East Fishkill development and manufacturing site. The 32-nm processes will include ultra low-k dielectrics, high-k, metal gates, strained silicon and second-generation immersion lithography technology. IBM will enter into 32-nm product qualification by year-end 2009 and move its high-k technology into production at the 45-nm node for processor products.

IBM announces the application of self-assembling nanotechnology to backend low k integration. The technique deployed by IBM causes a vacuum to form between the copper wires on a computer chip, allowing electrical signals to flow faster, while consuming less electrical power. The self-assembly process enables the nano-scale patterning required to form the gaps; this patterning is considerably smaller than current lithographic techniques can achieve. In chips running in IBM labs using the technique, the researchers have proven that the electrical signals on the chips can flow 35 percent faster, or the chips can consume 15 percent less energy compared to the most advanced chips using conventional techniques. The self-assembly process already has been integrated with IBM's state-of-the-art manufacturing line in East Fishkill, New York and is expected to be fully incorporated in IBM’s manufacturing lines and used in chips in 2009. More ...

IBM announces that it has started manufacturing Cell processor on a 65-nm Silicon-on-Insulator process in East Fishkill. The move to 65nm will provide higher speeds and lower power. For the moment the devices in the 65-nm process are targeted at blade server. More ...

IBM announces that the company has developed a 45 nm high k metal gate for its 45 nm node. IBM has inserted the technology into its semiconductor manufacturing line in East Fishkill without the need for major tooling or process changes. The technology was developed together with IBM's alliance partners AMD, Toshiba, and Sony. Incremental work leading up to this achievement had been published earlier by IBM in scientific journals and presented at chip technology conferences. IBM plans to publish the summary of this final achievement in a similar forthcoming venue. Source: IBM
The Register claims to have obtained a draft of the paper with the summary mentioned in the IBM press release.

At a press event in Santa Clara, process-development partners IBM, Chartered, Infineon and Samsung gave a glimpse into their 32-nm technology plans. The team is looking into several obvious technology candidates: high-k dielectric materials, metal gates, ultra low-k films and silicon germanium. 193 nm immersion litho with double patterning is a possibility, EUV rather unlikely. The ramp of the 32 nm node is planned for late 2009, early 2010, i.e. two years after the 45 nm ramp.

A paper in the journal "Science" by IBM reports the formation of an integrated logic circuit assembled on a single carbon nanotube. The researchers built a five-stage ring oscillator with 12 FETs side by side along the length of an individual carbon nanotube. A complementary metal-oxide semiconductor-type architecture was achieved by adjusting the gate work functions of the individual p-type and n-type FETs used. Source : Science

IBM announces at the 2005 Symposium for VLSI technology that it used selective silicon epitaxial growth to create PFETs in bulk silicon with a 110 surface orientation. The NFET transistors were laid out on silicon-on-insulator (SOI) with a 100 surface orientation. Both transistors were stressed nitride layers, the NFET with a tensile strain and the PFET with a compressive strain. The result was a 30 percent on-current boost for the PFET, and NFET performance that was the same as if the wafer was a conventional SOI wafer. IBM calls the approach HOT, for hybrid orientation technology. Source: EE Times

IBM announces that it has developed a new method of MPU manufacturing using a combination of SOI, strained silicon and copper wiring technologies. IBM is using this technique immediately in volume 90nm production at its 300mm manufacturing facility in East Fishkill, N.Y., turning out 64-bit PowerPC 970FX microprocessors. Source: Electronic News

IBM Semiconductor Research and Development Center and IBM Microelectronic Division present at the IEDM conference a technique to utilize different
crystal orientations for pFET (110 oriented surface) and for nFET (100 oriented surface) to increase the mobility of the holes and electrons, respectively. In another paper, IBM reports on strained MOSFETs which are built directly on insulator structures with no SiGe layer present under the strained Si channel (SSDOI). IBM presents also an ultra-thin SOI (UTSOI) device as an attractive choice for sub-10nm gate-length scaling.Source: IEDM

IBM discloses that it has developed two new, advanced chip-manufacturing techniques, including what it calls "strained-silicon directly on insulator" (SSDOI) and "hybrid-orientation technology" (HOT).

IBM has developed the world's first transistor based on SSDOI technology. The sub-60-nm, field-effect transistor provides high electron mobility, while eliminating the material and process integration problems with today's silicon-germanium (SiGe) technology. The SSDOI structure is created by transferring strained silicon grown epitaxially, layer by layer, on relaxed SiGe to a buried oxide layer. The SiGe layer was removed before fabricating the device.

In the so-called HOT technology, two substrates are combined in the same wafer for CMOS devices. This results in a 40 percent to 65 percent performance boost for CMOS devices, according to IBM. The CMOS is fabricated on hybrid substrate with different crystal orientations to achieve positively-charged field-effect transistor (PFETs) performance. A layer transfer process, block-level trench etch, and epitaxial regrowth are performed before conventional CMOS device process. An enhancement of 40-65 percent for the PFET was demonstrated on a 90-nm node CMOS technology. Source: SBN

IBM announces the first light emitter based on carbon nanotubes (CNT's). IBM's light emitter is a single nanotube, 1.4 nanometers in diameter, configured into a three-terminal transistor. The device is "ambipolar", i.e. electrons and holes are injected simultaneously from a drain electrode into a single carbon nanotube. When the electrons and holes meet in the nanotube, they neutralize each other and generate light. The report on this work "Induced Optical Emission from a Carbon Nanotube FET" by J.A. Misewich, R. Martel, Ph. Avouris, J.C. Tsang, S. Heinze, and J. Tersoff of IBM's T.J. Watson Research Center in Yorktown Heights, N.Y. is published in the May 2 issue of Science. For a copy of the full manuscript, please email or call (202) 326-6440 and request paper number 15 in the May 2 issue. (CNT's). Source: ""







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