Hitachi Ltd. and Mitsubishi Electric Corp. announce plans to merge large parts of their semiconductor business. Source: SBN
The new company official starts business under the name of Renesas. It will combine the non-dRAM parts of the business of Hitachi and Mitsubishi. Source: '
Renesas Technology Corp announces the development of an SOI (Silicon On Insulator) CMOS device technology with a new structure that achieves faster operation while reducing the operating voltage, and that will be an effective technology for next-generation microcomputers and SoC (system-on-a-chip) devices. Following trial fabrication of SRAM (static random access memory) in which this technology was applied to a 130 nm (nanometer) SOI CMOS process, test results show an approximately 20% reduction in lower-limit operating voltage from 0.6V to 0.5 V together with an approximately 35% improvement in operating speed. Details of the newly developed technology are as follows.
1. Device structure that allows dynamic threshold voltage control with no increase in element area or parasitic capacitance:
A "direct body contact technology" was developed whereby electrical contact is made to the body - the foundation of the transistor - in individual transistors. This structure makes it possible for the gate electrode that performs transistor on/off control and the body to be connected by a single contact. This structure was implemented using Renesas Technology's proprietary hybrid trench isolation technology, and includes the following features.
1.1. Dynamic threshold voltage control according to transistor operating state:
By forming a contact on the body, the previously fixed body potential can be made variable, and the transistor threshold voltage can be controlled dynamically according to the circuit configuration. For example, when the body and a gate electrode are connected, it is possible to lower the threshold voltage only when the transistor is turned on, increase the transistor on-current, improve the operating speed, and so forth.
1.2. No increase in area or parasitic capacitance:
Performing body potential control requires a terminal that connects to the body, and there have been problems in configuring this with conventional technologies.
a) With normal bulk silicon devices, a special well structure is necessary to prevent effects between adjacent transistors, resulting in an extremely large chip area.
b) Conventional SOI devices require a special shape in which the gate electrode area is large, with resultant problems of increased parasitic capacitance, deterioration of operating speed, and increased power consumption.
However, with the structure employing hybrid trench isolation:
a) individual transistors are isolated by totally eliminating the SOI layer, making a special well structure unnecessary, and
b) the terminal that connects the body is created by means of a partial isolation structure that leaves part of the SOI layer, making it possible to use a gate electrode with a conventional simple shape.
As a result, increases in chip area and parasitic capacitance are suppressed, and it is possible to control the body potential of individual transistors.
(2) SRAM cell structure enabling low-voltage, high-speed operation:
An SRAM cell structure was devised that uses elements with the structure described in (1) and enables low-voltage, high-speed operation. A structure was used whereby the threshold voltage of transistors comprising memory cells is lowered dynamically only when memory cell data is accessed.
As the current drive capability increases during access, high-speed operation is possible even at a low voltage. Moreover, as the threshold voltage is high in the non-access state - that is in the standby state - the standby current does not increase. Furthermore, use of the structure described in (1) makes it possible to form an SRAM memory cell with the new structure with virtually the nearly same area as a normal bulk silicon SRAM memory cell.