Plasma Technology for Advanced Devices

Clarycon News Archive: SAMSUNG

Samsung announces the completion of the development of a 4-Gbit DDR3 DRAM chip using a 50-nm manufacturing process. The memory operates at 1.35 volts and has a maximum data transmission speed of 1.6-Gbits per second.

Samsung announces that it is sampling a 16 Gb NAND flash memory with customers – the first NAND flash using 50 nanometer (nm) process technology. The first samples of this high density NAND flash memory have a multi-level cell (MLC) design with a 4Kbyte (KB) page size to enhance both its read and write features. The new 4KB page function improves the conventional 2KB paging system for MLC NAND flash to double the read speed, while increasing write performance 150%. Samsung plans to begin mass producing its 16Gb NAND flash memory in the first quarter of 2007. Source: SAMSUNG

Samsung announces that it has developed the industry’s first 40 nm memory device. The new 32 Gb NAND flash device is the first memory to incorporate a Charge Trap Flash (CTF) architecture.

The new CTF-based NAND flash memory increases the reliability of the memory by sharply reducing inter-cell noise levels. Its simpler structure also enables higher scalability which will eventually improve manufacturing process technology from 40 nm to 30 and even 20nm.

In each 32Gb device, the control gate in the CTF is only 20 percent as large as a conventional control gate in a typical floating gate structure. With CTF, there is no floating gate. Instead, the data is temporarily placed in a “holding chamber” of the non-conductive layer of the flash memory composed of silicon nitride (SiN). This results in a higher level of reliability and better control of the storage current. The CTF design is enabled through the use of a TANOS structure comprised of tantalum (metal), aluminum oxide (high k material), nitride, oxide and silicon. The use of a TANOS structure marks the first application of a metal layer coupled with a high k material to the NAND device.

Samsung today announces the start of the production of a 4GB solid state (SSD) which will serve as a high speed NAND flash cache for notebooks and PCs with Microsoft's upcoming Windows Vista operating system.

Samsung announces details of the the industry’s first 2-gigabit (Gb) DDR2 SDRAM manufactured on 80-nanometer (nm) process technology. Samsung’s DRAM technology includes a 3D transistor technology, recess channel array transistor (RCAT). To address the high performance features of the DDR2 specification, Samsung adopted a double poly gate technology, 20-angstrom level ultra thin oxide film process, and a triple-layer metal circuitry.

SAMSUNG presents at the IEDM conference a paper on MOSFET’s with an integrated
HfO2-Al2O3 laminate gate dielectric with CVD-TaN metal gate, claims the first fully integrated bulk FinFET SRAM cell, and demonstrates a fully working Triple Gate SRAM cell. Source: IEDM

Samsung announces an 80nm 512Mbit monolithic dRAM device. The new device incorporates Recess Channel Array Transistor (RCAT) technology to enhance data refresh features. The three-dimensional design significantly increases density, with a three-dimensional transistor to pair each capacitor in the DRAM circuitry. The device uses low-resistance tungsten gates for higher performance at low temperatures and a high-k oxide process for low voltage requirements beyond 1.5V. Source: Electronic News







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