Plasma Technology for Advanced Devices

TSMC agrees to become a core partner in IMEC's sub-45-nm CMOS research program. Source: IMEC

TSMC announces plans to deploy copper-interconnects, ultra low-k dielectrics and immersion lithography at the 45-nm node but casts doubts about the deployment of high k materials. The company believes that it can gain more improvements in transistor mobility by using a proprietary strained-silicon technology. Source:
EE Times

TSMC reports at the IEDM conference a 65 nm strained SOI technology with aggressively scaled slim spacer of 30 nm width for transistors with 40 nm gate length and a paper on process induced stress to inprove the performance of NMOS and PMOS devices simultaneously. Source: IEDM

In another setback for 157-nm lithography TSMC has cancelled its orders for 157-nm tools and will instead back immersion technology. TSMC and ASML are developing an immersion tool, based on ASML's 193-nm TwinScan platform. Source: Silicon Strategies

TSMC's announces that their roadmap calls for the use of silicon dioxide, high-k or both as the gate dielectric at the 65-nm node. The company will offer strained-silicon and silicon-on-insulator options at both 90 and 65 nm. Its strained-silicon offering is a "proprietary technology" that promises to reduce gate leakage by 14 percent. The company will not offer strained silicon in the first phase of its 90-nm rollout, but will introduce it at a later date if demand builds for the technology. Source: SBN



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