Plasma Technology for Advanced Devices

This list represents a collection of patents which could be of interest to visitors to The list was generated by searching the USPTO database for "plasma and etch" as well as "transistors". The final list was selected among the search results by the editor of this page. The search included the time frame of June and the first week of July 2004.

US Patent Number

Title / Assignee



Method for plasma etching a microelectronic topography using a pulse bias power

Silicon Magnetic Systems

A method is provided which includes pulsing power applied to a microelectronic topography between a high level and a low level during a plasma etch process. In particular, the high level may be sufficient to form etch byproducts at a faster rate than a rate of removal of the etch byproducts from the reaction chamber at the high level. In contrast, the low level may be sufficient to form etch byproducts at a rate that is less than a rate of removal of the etch byproducts at the low level. In this manner, an etched topography may be formed without an accumulation of residue upon its periphery. Such a method may be particularly beneficial in an embodiment in which the etch byproducts include a plurality of nonvolatile compounds, such as in the fabrication of a magnetic junction of an MRAM device, for example.


Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography

Hewlett-Packard Development Company

A method for fabricating sub-lithographic sized line and space features is disclosed. The method includes the use of conventional microelectronics processing techniques such as photolithographic patterning and etching, polysilicon deposition, polysilicon oxidation, polysilicon oxide etching, polysilicon wet and plasma etching, and chemical mechanical planarization. Polysilicon line features having a feature size that is greater than or equal to a lithography limit are oxidized in a plasma that includes an oxygen gas. The oxidation forms a sub-lithographic sized polysilicon core and an oxidized polysilicon mantel that includes portions along sidewall surfaces of the sub-lithographic sized polysilicon core that also have a sub-lithographic feature size. After planarization and a plasma etch that is selective to either the polysilicon or the oxidized polysilicon, a plurality of sub-lithographic sized line and space patterns are formed. Those line and space patterns can be used for an imprinting stamp for nano-imprint lithography.


Multi-core transformer plasma source

Applied Materials

A transformer-coupled plasma source using toroidal cores forms a plasma with a high-density of ions along the center axis of the torus. In one embodiment, cores of a plasma generator are stacked in a vertical alignment to enhance the directionality of the plasma and generation efficiency. In another embodiment, cores are arranged in a lateral array into a plasma generating plate that can be scaled to accommodate substrates of various sizes, including very large substrates. The symmetry of the plasma attained allows simultaneous processing of two substrates, one on either side of the plasma generator.


Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques


A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.


Nanotube permeable base transistor


A permeable base transistor (PBT) having a base layer including metallic nanotubes embedded in a semiconductor crystal material is disclosed. The nanotube base layer separates emitter and collector layers of the semiconductor material.


Method for selective trimming of gate structures and apparatus formed thereby


A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.


Multiple gate transistor employing monocrystalline silicon walls

Freescale Semiconductor

A semiconductor fabrication process and structure in which a dielectric structure is formed upon a substrate. Silicon is then deposited and processed to form a crystalline silicon wall that envelopes the dielectric structure and is physically and electrically isolated from the substrate. A gate dielectric film is formed over at least two surfaces of the silicon wall and a gate electrode film is formed over the gate dielectric. The gate electrode film is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall disposed on either side of the gate electrode may then be contacted to form source/drain structures. In this manner, the portion of the silicon wall covered by the gate electrode comprises a transistor channel region having multiple surfaces controlled by gate electrode.


Dual double gate transistor


The present invention provides a dual gate transistor and a method for forming the same that results in improved device performance and density. The present invention uses a double gate design to implement a dual gate transistor. A double gate is a gate which is formed on both sides of the transistor body. The present invention thus provides a transistor with two double gates in series that provide improved current control over traditional dual gate designs. The preferred embodiment of the present invention uses a fin type body with dual double-gates. In a fin type structure, the double gates are formed on each side of a thin fin shaped body, with the body being disposed horizontally between the gates.


Process for manufacturing transistors having silicon/germanium channel regions


A method of manufacturing an integrated circuit includes providing an amorphous semiconductor material including germanium, annealing the amorphous semiconductor material, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor.

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