Plasma Technology for Advanced Devices

Presented at SEMICON China 2004:

Technology Innovations and Process Integration for Sub-100nm Gate Patterning

Meihua Shen, Wilfred Pau, Nicolas Gani, Jianping Wen, Shashank Deshmukh, Thorsten Lill, Theodoros Panagopoulos and John Holland
Applied Materials Inc., 974 E. Arques Avenue, Sunnyvale CA 94086, USA

Jian Zhang, Hanming Wu and Guqing Xing
SMIC, Shanghai, China


This paper presents a brief overview of the Applied Materials, Inc.Centura« DPS« system, configured with silicon etch DPS II chamber, with emphasis on discussing tuning capability for CD uniformity control. It also presents the studies of etch process chemistry and film integration impact for an overall successful gate patterning development. Discussions will focus on resolutions to key issues, such as CD uniformity, line-edge roughness, and multilayer film etching integration.

I. Introduction

Several new factors are rendering gate patterning increasingly challenging as the industry moves toward the sub-100nm technology nodes. These are extremely tight CD control requirements (e.g., < 3nm 3 σ within wafer and < 2nm wafer to wafer for 90nm node), complications induced by 193nm resist, an ultra-thin gate dielectric layer (approximately10-15┼), and multiple film stacks involving different etch chemistries over a wide process region.

To meet these challenges, hardware and process must work together to ensure a successful gate patterning system. From the equipment side, the emphasis is on developing new technology and system integrations to meet two seemingly contradictory requirements: providing process flexibility or tuning capability over a wide process window, while maintaining precise control or repeatability of tool performance. From the process and integration side, the main focuses are on new process chemistry development, film integration, and resist material choices. The following will provide a brief overview of the recent technology and innovations addressing the above main elements of the gate patterning.

II. CD Control – The Technology Driver

A typical gate etch process involves multiple steps using different chemistries under different pressures. Hardware tuning knobs are required to provide flexibility to control uniformity over wide process region. Applied Materials DPS II silicon etch system contains three key tunable elements, a tunable inductive RF plasma source, a tunable gas delivery system and a tunable dual zone backside helium cooled electric-static-chuck (ESC)[1-3]. The schematics are shown in Fig. 1.

2.1 Tunable Plasma Source

The plasma source consists of a dual coil design with a divider capacitor splitting the current between inner and outer coils. The current ratio controls the ion flux distribution. Figure 2 shows the Ar+ flux distribution based on plasma modeling and the corresponding oxide etch rate for different current ratios. Ion flux and oxide etch rate become center high with higher inner/outer current ratio while the distribution is reversed when more current is channeled to outer coil.

2.2. Tunable Gas Delivery System

The tunable gas nozzle delivery system is designed to control the neutral flux distribution by adjusting the gas flow ratio between center and side of the gas injection inlet. The ratio correlates to the relative strength of convection vs. diffusion flow. Figure 3 shows the Cl2 gas velocity under different total flow and flow ratio based on flow simulation calculations. The gas velocity at a fixed chamber to nozzle distance can be altered dramatically through total gas flow as well as center/side flow ratio. As expected, gas velocity reaches highest at high gas flow under center only flow injection condition.

Gas flow dynamics not only impacts etch species distribution but also influences the by-products distribution (hence the passivation distribution)[4]. As a result, CD bias distribution across the wafer can be adjusted effectively through the flow ratio. Figure 4 shows the flow ratio effect on by-product distribution based on flow simulation calculation and the CD bias uniformity distribution on a Si wafer under the same plasma condition. SiClx by-products are depleted at the center of the wafer when the Cl2 gas flow is inject through the center of the nozzle since the high convection incoming flux swaps away the by-products in the center of the wafer effectively. The lack of passivation in the center results in smaller CD in the wafer center as shown in the bottom portion of Figure 4.

2.3. Two Complimentary Elements

It is important to notice that the etch rate uniformity can also be altered with different gas flow ratio because the incoming gas flux distribution is changed. Simultaneous adjustment of tunable RF source and tunable gas flow ratio are needed in order to obtain good etch rate and CD uniformity at the same time. For poly gate application, RF coil current ratio controls the etch rate uniformity while the gas flow ratio controls the CD uniformity. These two elements are relatively decoupled as illustrated in Fig. 5. Here the etch rate uniformity distribution changes from center slow at a lower inner/outer RF current ratio to near flat at higher inner/outer current ratio, but the CD uniformity distribution remains largely unaffected by changes in coil current ratio.

2.4. Dual Zone Backside Helium Cooled ESC

Dual zone backside Helium cooling of ESC is effective to modulate across wafer thermal gradient. Wafer temperature distribution can be adjust by applying different backside Helium pressure between the two zones as shown in figure 6. Center of the wafer become 5 0C hotter than the edge at 4 torr inner /12 Torr outer helium pressure setting while the center of the wafer become ~4 0C colder than the edge at 12 Torr inner/4 Torr outer pressure condition.

The ability to control the temperature profile through dual zone helium pressure is especially important for the CD uniformity near the edge of the wafer. Figure 7 shows the effect of CD distribution at different backside helium cooling pressure between inner and outer zone. By cooling the edge of the wafer through the backside Helium pressure (8torr inner/12torr outer), CD loss near the edge of the wafer tendency can be controlled.

III. Process and Film Integration

3.1 Hardmask Film Thickness Impact on Process Window

For sub-100nm gate etching, the following typical in-situ hard mask gate etch process flow (Fig. 8) has been adopted to balance the overall requirements for CD, gate oxide selectivity and line edge roughness. The all-in-one process scheme involves eight process steps in one chamber: BARC open, PR/BARC trimming, hardmask open, PR strip, polysilicon breakthrough step, poly main etch, poly softlanding and poly overetch. Each film stack is related to each other through different selectivity requirements. While the polysilicon and gate oxide film stack is determined by the design rule, the choice of hardmask thickness plays a crucial role in widening the overall gate etch process margin and process robustness.

Let us examine two examples where the hardmask is either too thick or too thin. When hardmask film is too thick, higher mask to resist selectivity process is required to open the hardmask especially when aggressive resist trimming is needed. Higher hardmask to resist selectivity process, however, results in thicker polymer deposition, which makes the subsequent resist strip difficult. Figure 9 shows the comparison of residue remaining after resist stripping when two different hardmask/PR selectivity processes are applied. No resist residues are observed with relative lean hardmask process while residues are seen with higher mask/resist selectivity mask open process.

If the hardmask film is too thin, while the mask open and resist strip process window margin are widened, the polysilicon etch step selectivity requirement become critical. Higher polysilicon to hardmask selectivity results in more silicon by-products passivation, which could degrade CD uniformity control. When the mask becomes too thin, even breakthrough step chemistry choice needs to be carefully screened to avoid mask breakdown. Figure 10 showed the comparison between a CF4 based chemistry breakthrough step and HBr based chemistry breakthrough step. Mask erosion was observed with the CF4 breakthrough step while the HBr breakthrough chemistry kept the mask in tact. An adequate hardmask film thickness appears to be around 50 to 70 nm for a typical 150 – 170 nm of polysilicon film stack.

Another aspect of film structure impact on process window lies in polysilicon morphology effect on gate oxide integrity control window. During polysilicon etch, multiple steps are used to balance the profile and to prevent thin gate oxide damage. A main etch with relatively low poly/HM selectivity process etches bulk portion of the film followed by a high selectivity softlanding step and a very high selective overtech processes. Frequently, there is a trade-off between selectivity and profile/CD uniformity since more passivation generated from highly selective process demands more stringent by-product distribution management. To achieve best profile and CD uniformity, main etch process usually is extended very close to the poly/oxide interface. If the polysilicon film grain boundary size reaches a few hundred Angstroms, main etch step needs to terminate earlier to avoid oxide punching through. Maintaining adequate control of polysilicon surface roughness can benefit both from device and process perspective.

3.2. BARC film and no-BARC film comparison

For 193 nm photolithography, either organic anti-reflection film (BARC) or dielectric anti-reflection (DARC) film can be used to pattern sub 100nm geometry features. DARC film can also be used as a part of hardmask. Two sets of wafers were prepared to examine the BARC film impact on etch performance, one set with 80 nm of BARC film and another set without BARC film but otherwise identical DARC/HM and poly film structure.

Figure 11 shows the resist trimming curves with BARC and without BARC film using same trimming/harmask/poly process. Trimming rate is near identical but the interception is different because of more CD loss during BARC open step. Poly profile and CD uniformity are also very similar between the two film stacks. It appears that addition of BARC film imposes no draw back from etch perspective. The process performance transparency between with BARC and without BARC film scheme makes it flexible for photolithography optimization. BARC film adhesion could provide better lithography quality between 193nm resist and underline film.

3.3. Line-Edge Roughness Improvement Through Etch Process

Line-edge roughness (LER) become a major concern when gate length shrink down to 20 to 40nm range. Etch process chemistry during BARC/trim and hardmask open step played a very important role in reducing LER. Through proper etch chemistry process optimization, pre-etch photoresist LER can be reduced dramatically [5]. Figure 10 shows an example of LER improvement after etching. LER improved from 9nm to about 5-6nm in this case.

IV. Summary

Three key tunable elements in Applied Materials Inc. Centura« DPSII« silicon etch system provide flexibility and control capability to meet the sub 100nm gate patterning challenging. On-board OCD metrology, advanced EyeD™ endpoint system and Advanced Process Control monitoring system ensure the precise and repeatability of tool performance. Along with system and chamber technology innovation, process development and device film integration advancement are equally important in order to deliver an successful gate patterning system.


1. Mike Barnes et al., Inductively coupled plasma source with controllable power deposition, US Patent 6,507,155.

2. John Holland et. al, 48th AVS Symposium, San Francisco, CA, 2001. Also US Patents 5,980,686 and 6,090,210.

3. Theodoros Panagopoulos and et al, 2003 GEC Conference, San Francisco.

4. M. Kiehlbauch, D.Graves, J.Vac.Sci. Tech A. 21, 116,2003

5. M. Shen et al, SEMACON Korea Technical Symposium, 2003

Figure 1: Tunable coil, tunable gas nozzle and tunable backside helium cooled ESC.

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Figure 2: Top: Ar+ flux distribution as function center/edge coil ratio. Bottom: Oxide etch rate as function coil ratio.

Figure 3: Flow simulation of Chlorine gas velocity distributions as function of the distance from the gas nozzle at 100 sccm and 300 sccm total flow with different center/side gas ratio.

Figure 4: Top – flow simulation of SiCl by-products distribution at 5mt/500Ws/100Wb/300sccmCl2. Bottom – experimental CD bias data on Si wafer under the same condition.

Figure 9: Residue comparison after resist stripping under porcess conditions with higher (top) and lower (bottom) hardmask/resist selectivity.

Figure 5: Top – Etch rate uniformity at low and high inner/out RF current ratio. Bottom - CD bias distribution across wafer at low and high inner/out RF current ratio.

Figure 10: Mask erosion comparison with CF4 (top) and HBr (bottom) poly breakthrough step.

Figure 6: Wafer temperature measurement under 4torr inner/12 torr outer He pressure (top) and 12 torr inner/4 torr outer He pressure (bottom).

Figure 11: Trimming curve comparison between BARC film and without BARC film scheme.

Figure 7: CD distribution at two different backside helium pressure settings.

Figure 8: Process flow of typical in-situ HM poly gate etch.

Figure 12: Top-down SEMs of pre and post gate etch LER comparison.