Plasma Technology for Advanced Devices

Thin Gate Oxide Behavior During Overetch Step

In this study, in-situ reflectometry was used to investigate the behavior of very thin gate oxides during exposure to HBr / O2 based plasmas which are typically being used in gate overetch recipes. A wavelength of 365 nm was chosen for the experiments (slide 1).

Slide 2 shows a typical signal of the light which was reflected from the poly-SI on gate oxide stack. It shows three distinct areas as seen in the corresponding SEM's of the surface morphology: a phase of poly-Si removal followed by gate oxide removal and gate oxide punch through.

A more detailed analysis shows the presence of a plateau after the clearance of the poly-Si which can be interpreted as a point in time when the gate oxide is exposed to the plasma but still intact. The length of this plateau represents the gate oxide life time. It was established in numerous experiments that this plateau is followed by a gradual change in the reflected ligth intensity where the signal rises or falls in alinear manner depending on the process conditions. It is assumed that this eriod in time corresponds to the co-existance of bulk silicon and oxide islands.After this transition, the signal flattens out because the surface is comprised of bulk silicon only. Slide 3 shows the signals for five different gate oxide thicknesses.

The analysis of the gate oxide life time and the transition time (gate oxide islands) as a function of the gate oxide thickness shows that the gate oxide life time decreases linearly with the gate oxide thickness. From the slope, a gate oxide etch rate of 113 A/min can be derived. The transition time does not significantly change with the gate oxide thickness because it is most likely related to the initial poly-Si roughness which was equal for all five samples (slide 4).

In another experiment, test chips were placed on carrier wafers which different areas of exposed silicon to simulate different loadig conditions. Slide 5 illustrates that the gate oxide life time is also a functiion of the silicon loading.

Slide 6 illustrates, that the gate oxide life time is dramatically reduced for conditions that are characterized by larger ion fluxes. The gate oxide life time is dropping faster than 1/W for an increasing source power and the silicon etch rate increase proportionally with the source power. This means that the selectivity to the gate oxide is reduced at higher source powers. The surprising result is that this effect is not compensated by the reduced ion energy.

It is known, that plasma oxidation can occur for thin gate oxides (< 50 ). This would explain that good gate oxide selectivities can be achieved for higher ion energies since positively charged oxygen ions can pepentrate the gate oxide (slide 7).

TEM cross section reveal that the surface oxidation of the gate oxide / silicon interface by the presence of gate oxid"bending" or "recessing". This effect has to be minimized for advanced transistor devices in order to avoid large channel resistances (slide 8).


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